ACtE08 · Chapter 8Demo2 · Set 2🏛️ Past Licensure QuestionID: d531f57c
In computer architecture and memory hierarchy management, what does the acronym TLB stand for?
In computer architecture and memory hierarchy management, what does the acronym TLB stand for?
Multiple Choice Options
- A✓ Correct Option
Translation Lookaside Buffer
- B
Time Loop Buffer
- C
Table Load Balancer
- D
Transfer Logic Buffer
Detailed Technical Solution & Explanation
A Translation Lookaside Buffer (TLB) is a dedicated high-speed hardware associative cache located inside the Memory Management Unit (MMU). It stores the most recently used virtual-to-physical page table mappings, avoiding slow multi-level main memory page table walks during address translation.
Option Analysis:
•
Option A (Translation Lookaside Buffer): Correct; standard architectural term in virtual memory systems.
•
Option B (Time Loop Buffer): Incorrect; fictitious term.
•
Option C (Table Load Balancer): Incorrect; database or network terminology.
•
Option D (Transfer Logic Buffer): Incorrect; fictitious term.
Reference: Demo2 · Set 2NEC Licensure Syllabus