AExE02 · Chapter 2Basic Electrical & Electronics🏛️ Past Licensure QuestionID: 6a4ff26f
In digital hardware design, when using a process to model a purely combinational circuit, which signals must be included in the sensitivity list?
In digital hardware design, when using a process to model a purely combinational circuit, which signals must be included in the sensitivity list?
Multiple Choice Options
- A
outputs of the circuit
- B✓ Correct Option
inputs of the circuit
- C
both a and b
- D
no signal should be in the sensitivity list
Detailed Technical Solution & Explanation
In VHDL/Verilog hardware description, a process modeling pure combinational logic must re-evaluate whenever any input signal changes. Therefore, its sensitivity list must include all input signals to the circuit to avoid generating unwanted latches.
Option Analysis:
•
Option A (outputs of the circuit): Incorrect. Placing outputs in the sensitivity list causes infinite simulation loops.
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Option B (inputs of the circuit): Correct. All input signals must appear in the sensitivity list for pure combinational evaluation.
•
Option C (both a and b): Incorrect.
•
Option D (no signal should be in the sensitivit...): Incorrect. A process without a sensitivity list must use wait statements.
Reference: Mock Test 05NEC Licensure Syllabus