ACtE05 · Chapter 5Networks & Security🏛️ Past Licensure QuestionID: 0917305d
In the 8085 microprocessor architecture, the non-maskable TRAP interrupt is triggered by which electrical signal condition?
In the 8085 microprocessor architecture, the non-maskable TRAP interrupt is triggered by which electrical signal condition?
Multiple Choice Options
- A
Negative level sensitive only
- B
Positive level sensitive only
- C✓ Correct Option
Both edge-triggered (rising edge) and level-sensitive (high level)
- D
Edge-triggered only
Detailed Technical Solution & Explanation
In the Intel 8085 microprocessor, TRAP is a unique non-maskable interrupt that is both edge-triggered and level-sensitive (a rising edge followed by a sustained high level until sampled). This dual mechanism prevents false triggering due to electrical noise while ensuring the interrupt request is reliably captured.
Option Analysis:
•
Option A (Negative level sensitive): Incorrect triggering mode.
•
Option B (Positive level sensitive): RST 7.5 / INTR use purely level or edge triggers.
•
Option C (Both edge-triggered and level-sensitive): Correct; TRAP requires a positive transition followed by a high level to avoid noise glitches.
•
Option D (Edge-triggered only): RST 7.5 is purely edge-triggered, whereas TRAP combines edge and level sensitivity.
Reference: Demo2 · Set 2NEC Licensure Syllabus